Memory devices are typically provided in many data processing systems as semiconductor integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), flash memory, and resistance variable memory, among others.
Conventional memory systems typically consist of one or more memory devices, such as DRAMs, mounted on a Printed Circuit Board (PCB) called a Dual In-line Memory Module (DIMM). The memory system is in communication with a memory control subsystem or Central Processing Unit (CPU) or microprocessor. In some configurations, the memory controller is physically subsumed into the same physical chip as the processor. In other configurations the memory controller may be just one of many logical components comprising a Memory Controller Hub (MCH). A memory controller hub typically supports completely separate and distinct memory address spaces, often using different types of semiconductor memory for different purposes. For example, a memory controller may support the use of video DRAM for graphics applications, flash memory for disk-drive acceleration, and commodity DRAM as the processor's main external memory.
Many computer systems are configured to create virtual memory assigned to specific processors, specific processes, and combinations thereof. Current software-based mechanisms for providing machine virtualization (e.g., “hypervisors”) provide a relatively insecure mechanism for dividing machine resources among different operating systems. Some hypervisors, most notably those in IBM mainframes, provide hardware enforcement for some of these mechanisms. Even the x86 architecture includes CPU rings for describing the privilege of instructions. Some software hypervisors like VMWARE may be built upon these rings. Some machines may provide hardware “domains” within a single large-scale Symmetric Multiprocessor (SMP) or large-scale distributed systems to allow for multiple instances of the operating system to run on the same hardware platform and provide hardware protection from interference among domains. These types of systems, however, only enable domain-level allocation of resources at the board level. Reconfiguration at the hardware-level is typically coarse-grain (e.g., requiring both processor and memory resources to be allocated together). Reconfiguration at the software level is typically fine-grain, but poorly enforced.
There is currently an industry trend towards “disaggregation” within datacenters, in which processor, memory, and storage resources are allocated in physical units (typically called “sleds”) and interconnected via datacenter-scale networks. These resources are accessed at high cost in terms of resources, latency, and throughput via typical network protocols, often TCP/IP. While these types of disaggregated systems enable a somewhat improved balancing of resources in that memory resources do not have to be allocated with processor resources (as was the case prior to disaggregation, adding a new memory controller or disc controller required the addition of another CPU and Operating System (OS) instance), which still incurs high overhead. Network processing alone requires significant firmware and embedded control; complex-protocols impose latency overhead and bandwidth restrictions; etc. Typically, four orders of magnitude in performance or more may be lost in these configurations. In addition, these disaggregated systems represent coarse-grain computer configurations.